A Reliable Wafer-level Chip Scale Package (wlcsp) Technology

In conventional WLCSP process, after defining the under bump metal (UBM) layer, a solder ball is dropped in the UBM opening. A subsequent thermal reflow cycle melts the solder ball and cools it in a well defined shape on top of the UBM layer. One draw back of this technology is the fracture or cracking of passivation film that may occur during the solder ball reflow process. The cracks in the passivation expose the underlying semiconductor devices to the ambient environment. Such cracks result in long term reliability problems or complete failure depending on the extent of the exposure to harmful ambient. In this paper, we systematically analyze the problem of passivation cracking and present a WLCSP process that is resistant to cracking during solder flow and subsequent multiple reflow steps. ANSYS thermo-mechanical finite element modeling software is used to model the WLCSP structure and process flow to evaluate stress and deformation at various points across the device structure. Contour plots clearly highlight the high stress regions and pinpoint the potential failure region. The use of ANSYS software in optimizing process parameters, and predicting reliability is presented. The experimental results confirm our simulation results and we conclude by presenting an optimized process that is resistant to passivation cracking and resulting failures.